Module Compteur Gray en Verilog – Générateur de Code Gray 4 bits

Conception

module gray_ctr # (
  parameter N = 4
) (
  input clk,
  input rstn,
  output reg [N-1:0] out
);
  reg [N-1:0] q;
  always @ (posedge clk) begin
    if (!rstn) begin
      q <= 0;
      out <= 0;
    end else begin
      q <= q + 1;
      `ifdef FOR_LOOP
      for (int i = 0; i < N-1; i= i+1) begin
        out[i] <= q[i+1] ^ q[i];
      end
      out[N-1] <= q[N-1];
      `else
      out <= {q[N-1], q[N-1:1] ^ q[N-2:0]};
      `endif
    end
  end
endmodule

Testbench

module tb;
  parameter N = 4;
  reg clk;
  reg rstn;
  wire [N-1:0] out;
  gray_ctr u0 ( .clk(clk), .rstn(rstn), .out(out) );
  always #10 clk = ~clk;
  initial begin
    {clk, rstn} <= 0;
    $monitor ("T=%0t rstn=%0b out=0x%0h", $time, rstn, out);
    repeat(2) @ (posedge clk);
    rstn <= 1;
    repeat(20) @ (posedge clk);
    $finish;
  end
endmodule

Journal de simulation

ncsim> run
T=0 rstn=0 out=0xx
T=10 rstn=0 out=0x0
T=30 rstn=1 out=0x0
T=50 rstn=1 out=0x1
T=70 rstn=1 out=0x3
T=90 rstn=1 out=0x2
T=110 rstn=1 out=0x6
T=130 rstn=1 out=0x7
T=150 rstn=1 out=0x5
T=170 rstn=1 out=0x4
T=190 rstn=1 out=0xc
T=210 rstn=1 out=0xd
T=230 rstn=1 out=0xf
T=250 rstn=1 out=0xe
T=270 rstn=1 out=0xa
T=290 rstn=1 out=0xb
T=310 rstn=1 out=0x9
T=330 rstn=1 out=0x8
T=350 rstn=1 out=0x0
T=370 rstn=1 out=0x1
T=390 rstn=1 out=0x3
T=410 rstn=1 out=0x2
Simulation complete via $finish(1) at time 430 NS + 0