Détecteur de séquence Verilog : Construire un FSM fiable pour reconnaissance de motif

Exemple très courant de machine d'états finis (FSM) : détecteur de séquence où le matériel doit détecter quand un motif fixe apparaît dans un flux de bits binaires en entrée.

Exemple

Détecteur de séquence "1011" :

module det_1011 (input clk, input rstn, input in, output out);
parameter IDLE = 0, S1 = 1, S10 = 2, S101 = 3, S1011 = 4;
reg [2:0] cur_state, next_state;
assign out = cur_state == S1011 ? 1 : 0;
always @ (posedge clk) begin
    if (!rstn) cur_state <= IDLE;
    else cur_state <= next_state;
end
always @ (cur_state or in) begin
    case (cur_state)
        IDLE:  begin if (in) next_state = S1; else next_state = IDLE; end
        S1:    begin if (in) next_state = IDLE; else next_state = S10; end
        S10:   begin if (in) next_state = S101; else next_state = IDLE; end
        S101:  begin if (in) next_state = S1011; else next_state = IDLE; end
        S1011: begin next_state = IDLE; end
    endcase
end
endmodule

Testbench

module tb; reg clk, in, rstn; wire out; reg [1:0] l_dly; reg tb_in; integer loop = 1;
always #10 clk = ~clk;
det_1011 u0 (.clk(clk), .rstn(rstn), .in(in), .out(out));
initial begin clk <= 0; rstn <= 0; in <= 0; repeat (5) @ (posedge clk); rstn <= 1;
// Pattern dirigé
@(posedge clk) in <= 1; @(posedge clk) in <= 0; @(posedge clk) in <= 1; @(posedge clk) in <= 1; // Pattern complet
@(posedge clk) in <= 0; @(posedge clk) in <= 0; @(posedge clk) in <= 1; @(posedge clk) in <= 1;
@(posedge clk) in <= 0; @(posedge clk) in <= 1; @(posedge clk) in <= 1; // Pattern à nouveau
// Stimulus aléatoire
for (int i = 0; i < loop; i++) begin l_dly = $random; repeat (l_dly) @ (posedge clk); tb_in = $random; in <= tb_in; end
#100 $finish; end
endmodule

Simulation Log :

ncsim> run T=10 in=0 out=0 T=30 in=0 out=0 T=50 in=0 out=0 T=70 in=0 out=0 T=90 in=0 out=0
T=110 in=1 out=0 T=130 in=0 out=0 T=150 in=1 out=0 T=170 in=1 out=0 T=190 in=0 out=1
T=210 in=0 out=0 T=230 in=1 out=0 T=250 in=1 out=0 T=270 in=0 out=0 T=290 in=1 out=0
T=310 in=1 out=0 T=330 in=1 out=1 T=350 in=1 out=0 T=370 in=1 out=0 T=390 in=1 out=0
Simulation complete via $finish(1) at time 410 NS + 0

Il y a un bug dans la conception. Saurez-vous le trouver ?

Maîtriser les blocs generate Verilog : Instanciation dynamique et conception conditionnelle Détecteur de motif Verilog : Détection de séquence avancée en FPGA

Verilog